SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Channel 1/3 Task File Configuration + Status
Address Offset: B0H
Access Type: Read/Write
Reset Value: 0x6515_0101
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
This register defines the task file configuration and status register for Channel 1/3 in the SiI3114. The register bits
are also mapped to Base Address 5, Offset E0H.See “Channel X Task File Configuration + Status” section on
page 65 for bit definitions.
BA5 Indirect Address
Address Offset: C0H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Address
00
This register permits the indirect addressing of registers normally referenced using Base Address 5. Any register
that is not accessible by any means other that via Base Address 5 is indirectly addressable. Bits 1 and 0 of the
Indirect Address must always be written with zeroes. The following BA5 address ranges are not indirectly
accessible, but are accessible either in Configuration Space or via other Base Address registers: 00–0CH, 80–
8CH, C0–CCH, 200–20CH, 280–28CH, 2C0–2CCH.
BA5 Indirect Access
Address Offset: C4H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
As defined for indirectly accessed register
This register provides the indirect access addressed by the BA5 Indirect Address register. The use of indirect
access must be enabled by setting bit 1 of the Configuration register (40H).
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
