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SII1161CTU 参数 Datasheet PDF下载

SII1161CTU图片预览
型号: SII1161CTU
PDF下载: 下载PDF文件 查看货源
内容描述: 的PanelLink接收机 [PanelLink Receiver]
分类和应用: 接收机
文件页数/大小: 46 页 / 379 K
品牌: SILICONIMAGE [ Silicon image ]
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SiI 1161 PanelLink Receiver  
Data Sheet  
June 2005  
General Description  
Features  
The SiI 1161 receiver uses PanelLink Digital  
technology to support high-resolution displays up to  
UXGA (25-165MHz). This receiver supports up to true  
color panels (24 bits per pixel, 16M colors) with both  
one and two pixels per clock.  
Supports 10 meter cables at UXGA speed  
I2C port for dynamic optimization of settings to  
compensate for long cables and/or poor quality  
transmitters  
Flexible output drive controls to optimize timings  
for all possible configurations  
3.3V operation  
Time staggered data output for reduced ground  
bounce and lower EMI  
Sync Detect feature for DVI “Hot Plugging”  
ESD tolerant to 5kV (HBM) on all pins  
Compliant with DVI 1.0  
Guaranteed interoperability with DVI-compliant  
transmitters  
Low power standby mode; automatic entry into  
standby mode with clock detect circuitry  
Pb-free packaging (see page 41).  
All PanelLink products are designed on a scaleable  
CMOS architecture, ensuring support for future  
performance enhancements while maintaining the  
same logical interface. System designers can be  
assured that the interface will be stable through a  
number of technology and performance generations.  
PanelLink Digital technology simplifies PC and display  
interface design by resolving many of the system level  
issues associated with high-speed mixed signal  
design, providing the system designer with a digital  
interface solution that is quicker to market and lower in  
cost.  
SiI 1161 Pin Diagram  
ODD 8-bits GREEN  
ODD 8-bits BLUE  
ODD 8-bits RED  
OGND  
QO23  
OVCC  
AGND  
RX2+  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
QO1  
QO0  
HSYNC  
VSYNC  
DE  
RX2-  
OGND  
ODCK  
OVCC  
CTL3  
CTL2  
CTL1  
GND  
OUTPUT  
CLOCK  
AVCC  
AGND  
AVCC  
RX1+  
SiI 1161  
RX1-  
100-Pin  
TQFP  
AGND  
AVCC  
AGND  
RX0+  
VCC  
QE23  
QE22  
QE21  
QE20  
QE19  
QE18  
QE17  
QE16  
OVCC  
OGND  
QE15  
QE14  
(Top View)  
RX0-  
AGND  
RXC+  
RXC-  
AVCC  
EXT_RES  
PVCC  
PGND  
MODE  
SCL  
(OCK_INV)  
PWR  
MGMT  
CONFIG. PINS  
EVEN 8-bits BLUE  
EVEN 8-bits GREEN  
SiI-DS-0096-D  
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