SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit
reflects IDE0 interrupt line.
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Bit [17]: PBM Error (R/W1C) – PCI Bus Master Error – IDE0. This bit set indicates that a PCI bus error
occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI
Configuration space.
Bit [16]: PBM Active (R) – PCI Bus Master Active – IDE0. This bit set indicates that the SiI 0680A is currently
active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have
completed or PBM Enable bit is not set.
Bit[15] : IDE Watchdog Timer Status ( R ) – This bit is an Ored result of bit 12 in IDE0 Task File Timing +
Configuration + Status and bit 12 of IDE1 Task File Timing + Configuration + Status registers. When set indicates
that either IDE0 or IDE1 Watchdog timer has expired.
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Bit[14] : IDE1 Interrupt Status ( R ) – This bit is a copy of Bit[18] IDE1 DMA Completion Interrupt in PCI Bus
Master – IDE1.
Bit [13:08]: Software Data (R/W) – System Software Data Storage. This bit field is used for read/write data
storage by the system. The properties of this bit field are detailed below.
Bit Location
[13:12]
Default
XXB
Description
Not cleared by any reset
[11:10]
00B
Cleared by PCI reset
[09:08]
XXB
Cleared only by a D0-D3 power state change
Table 9-8: Software Data Byte, Base Address 5, Offset 00H
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Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from IDE0 to system memory. This bit is cleared to specify a DMA read operation from system
memory to an IDE0 device.
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Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – IDE0. This bit is set to enable PCI bus master
operations for IDE Channel #0. PCI bus master operations can be halted by clearing this bit, but will erase all
state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be
aborted and the data discarded. While this bit is set, accessing IDE0 Task File or PIO data registers will be
terminated with Target-Abort.
9.7.2 PRD Table Address – IDE0
Address Offset: 04H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE0
This register defines the PRD Table Address register for IDE Channel #0 in the SiI 0680A. The register bits are defined below.
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Bit [31:02]: PRD Table Address (R/W) – Physical Region Descriptor Table Address. This bit field defines the
Descriptor Table base address.
Bit [01:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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