SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7 Internal Register Space – Base Address 5
These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows:
R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI Memory space. The
Base Address 5 can be disabled by setting input BA5_EN to low
Address
Offset
Register Name
Access
Type
31
16
15
00
00H
Reserved
Reserved
PCI Bus Master
Status – IDE0
Software Data
PCI Bus Master
Command – IDE0
R/W
04H
08H
PRD Table Address – IDE0
R/W
R/W
PCI Bus Master
Status – IDE1
Reserved
PCI Bus Master
Command – IDE1
0CH
10H
PRD Table Address – IDE1
PCI Bus Master Software Data
R/W
R/W
PCI Bus Master
Status – IDE1
PCI Bus Master
Command2 –
IDE0
Status2 – IDE0
14H
18H
Reserved
-
Reserved
PCI Bus Master
Status2 – IDE1
Reserved
PCI Bus Master
Command2 –
IDE1
R/W
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
40H
Reserved
-
PRD Address – IDE0
PCI Bus Master Byte Count – IDE0
PRD Address – IDE1
PCI Bus Master Byte Count – IDE1
Reserved
R
R
R
R
-
Reserved
-
Reserved
-
-
Reserved
FIFO Valid Byte Count – IDE0
FIFO Valid Byte Count – IDE1
System Configuration Status
FIFO Wr Request
Control – IDE0
FIFO Rd Request
Control – IDE0
R/W
44H
FIFO Wr Request
Control – IDE1
FIFO Rd Request
Control – IDE1
R/W
48H
4CH
50H
54H
System Command
R/W
R/W
R/W
R/W
System Software Data
FLASH Memory Address – Command and Status
Reserved
Flash Memory
Data
58H
EEPROM Memory Address – Command and Status
Reserved EEPROM Memory
R/W
R/W
5CH
Data
60H
FIFO Port – IDE0
R/W
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
69
SILICONIMAGE [ Silicon image ]
