SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.7 PRD Address – IDE0
Address Offset: 20H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Address
This register reflects the current DMA address and uses for diagnostic purposes only.
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Bit [31:00]: PRD Address (R) – This field is the current DMA0 Address.
9.7.8 PCI Bus Master Byte Count – IDE0
Address Offset: 24H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Byte Count High
Byte Count Low
This register defines the byte count register in the PCI bus master logic for IDE Channel #0 in the SiI 0680A. The register bits
are defined below.
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Bit [31]: End of Table (R). This bit set indicates that this is the last entry in the PRD table.
Bit [30:16] Byte Count High (R). This bit field is the PRD entry byte count extension for Large Block Transfer
Mode. Under generic mode, this bit field is reserved and returns zeros on a read.
•
Bit [15:00] Byte Count Low (R). This bit field reflects the current DMA0 byte count value.
9.7.9 PRD Address – IDE1
Address Offset: 28H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Address
This register reflects the current DMA1 Address and uses for diagnostic purposes only.
•
Bit [31:00]: PRD Address (R) – This field is the current DMA1 Address.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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