SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
Address
Offset
Register Name
Access
Type
31
16
15
00
CCH
D0H
IDE1 Read Ahead Data
R/W
R/W
IDE1 TF Starting
Sector Number2
IDE1 TF
Sector
IDE1 TF
Reserved
Count2
Features2 IDE1
TF Error2
D4H
IDE1 TF
IDE1 TF
IDE1 TF Cylinder IDE1 TF Cylinder
R/W
Cmd+Sts2
Device+Head2
High2
Low2
D8H
DCH
E0H
Reserved
IDE1 Virtual DMA/PIO Read Ahead Byte Count
IDE1 TF Timing IDE1 Config IDE1
-
R/W
R/W
Cmd
+ Status
+ Status
E4H
E8H
ECH
F0H
F4H
IDE1 Device 1 PIO Timing
IDE1 Device 0 PIO Timing
IDE1 Device 0 DMA Timing
IDE1 Device 0 UDMA Timing
R/W
R/W
R/W
R/W
R/W
IDE1 Device 1 DMA Timing
IDE1 Device 1 UDMA Timing
IDE1 Test Register
Reserved
IDE1 Data
Transfer Mode
F8H
Reserved
Reserved
-
-
FCH
Table 9-7: SiI 0680A Internal Register Space – Base Address 5
9.7.1 PCI Bus Master – IDE0
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_XX00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Software
Reserved
This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. The register bits are defined below.
•
•
Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
•
•
Bit [22]: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
•
•
Bit [20:19]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18]: IDE0 DMA Comp (R/W1C) – IDE0 DMA Completion Interrupt. During write DMA operation, This bit set
indicates that the IDE0 interrupt has been asserted and all data has been written to system memory. During
Read
DMA,
This
bit
set
indicates
that
the
IDE0
interrupt
has
been
asserted.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
71
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