SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
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Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from IDE0 to system memory. This bit is cleared to specify a DMA read operation from system
memory to an IDE0 device.
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Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – IDE0. This bit is set to enable PCI bus master
operations for IDE Channel #0. PCI bus master operations can be halted by clearing this bit, but will erase all
state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be
aborted and the data discarded. While this bit is set, accessing IDE0 Task File or PIO data registers will be
terminated with Target-Abort.
9.7.6 PCI Bus Master2 – IDE1
Address Offset: 18H
Access Type: Read/Write
Reset Value: 0x0008_xx00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Reserved
This register defines the second PCI bus master register for IDE Channel #1 in the SiI 0680A. The system must access these
register bits through this address to enable the Large Block Transfer Mode.
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Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that both IDE channels can operate as PCI bus master at any time.
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Bit [22]: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [21]: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect. The
device is always capable of DMA as a PCI bus master.
Bit [20]: IDE1 Watchdog (R ) . This bit is a copy of bit 12 in IDE1 Task File Timing + Configuration + Status
register. Refer to chapter 9.7.47 for detail information.
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Bit [19] : IDE1 Buffer empty (R). This bit set indicates IDE1 FIFO is empty.
Bit [18]: IDE1 DMA Comp (R/W1C) – IDE1 DMA Completion Interrupt. During write DMA operation, this bit set
indicates that the IDE1 interrupt has been asserted and all data has been written to system memory. During
Read
DMA,
this
bit
set
indicates
that
the
IDE1
interrupt
has
been
asserted.
This bit must be W1C by software when set during DMA operation (bit 0 is set). During normal operation, this bit
reflects IDE1 interrupt line.
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Bit [17]: PBM Error (R/W1C) – PCI Bus Master Error – IDE1. This bit set indicates that a PCI bus error
occurred while the SiI 0680A was bus master. Additional information is available in the PCI Status register in PCI
Configuration space.
Bit [16]: PBM Active (R) – PCI Bus Master Active – IDE1. This bit set indicates that the SiI 0680A is currently
active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data transfers have
completed or PBM Enable bit is not set.
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•
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Bit [15:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from IDE1 to system memory. This bit is cleared to specify a DMA read operation from system
memory to an IDE1 device.
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•
Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – IDE1. This bit is set to enable PCI bus master
operations for IDE Channel #1. PCI bus master operations can be halted by clearing this bit, but will erase all
state information in the control logic. If this bit is cleared while the PCI bus master is active, the operation will be
aborted and the data discarded. While this bit is set, accessing IDE1 Task File or PIO data registers will be
terminated with Target-Abort.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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