SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.6 Internal Register Space – Base Address 4
These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows:
R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space.
Address
Offset
Register Name
Access
Type
31
16
15
00
00H
Reserved
Reserved
PCI Bus Master
Status – IDE0
Software Data
PCI Bus Master
Command – IDE0
R/W
04H
08H
PRD Table Address – IDE0
R/W
R/W
PCI Bus Master
Status – IDE1
Reserved
PCI Bus Master
Command – IDE1
0CH
PRD Table Address – IDE1
Table 9-6: SiI 0680A Internal Register Space – Base Address 4
R/W
9.6.1 PCI Bus Master – IDE0
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_XX00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Software
Reserved
This register defines the PCI bus master register for IDE Channel #0 in the SiI 0680A. See Section 9.7.1 for bit definitions.
9.6.2 PRD Table Address – IDE0
Address Offset: 04H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – IDE0
This register defines the PRD Table Address register for IDE Channel #0 in the SiI 0680A. The register bits are also mapped
to PCI Configuration Space, Offset 74H and Base Address 5, Offset 04H. See Section 9.7.2 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
67
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