SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.4 Internal Register Space – Base Address 2
These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows:
R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space.
Address
Offset
Register Name
Access
Type
31
16
15
00
00H
04H
IDE1 TF Starting
Sector Number
IDE1 TF
Sector IDE1 TF Features
IDE1 TF Error
IDE1 TF Data
R/W
R/W
Count
IDE1 TF
Command+Status
IDE1 TF
Device+Head
IDE1 TF
Cylinder High
IDE1 TF Cylinder
Low
Table 9-4: SiI 0680A Internal Register Space – Base Address 2
9.4.1 IDE1 Task File Register 0
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Starting Sector
Number
IDE1 Task File Sector Count
IDE1 Task File Features (W)
IDE1 Task File Error (R)
IDE1 Task File Data
This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset C0H. See Section 9.7.39 for bit definitions.
9.4.2 IDE1 Task File Register 1
Address Offset: 04H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Command + Status
IDE1 Task File Device+Head
IDE1 Task File Cylinder High
IDE1 Task File Cylinder Low
This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset C4H. See Section 9.7.40 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
65
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