SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
1.10 PCI Configuration Space
This section describes how the PCI-680 implements the required PCI configuration register space. The intent is to provide an
appropriate set of configuration registers that satisfy the needs of current and anticipated system configuration mechanisms,
without specifying those mechanisms or otherwise placing constraints on their use. These registers allow for:
•
•
•
Full device relocation (including interrupt binding)
Installation, configuration, and booting without user interventions
System address map construction by device-independent software
Bit
Number
Bit
31
11 10
8 7
2
1
0
Number
Don’t Care
3-Bit
Function
Number
6-Bit
Register
Number
2-Bit
Type
Number
Figure 1-2: Address Lines During Configuration Cycle
PCI-680 only responds to Type 0 configuration cycles. Type 1 cycles, which pass a configuration request on to another PCI
bus, are ignored.
The address phase during a PCI-680 configuration cycle indicates the function number and register number being addressed
which can be decoded by observing the status of the address lines AD[31:0].
The value of the signal lines AD[7:2] during the address phase of configuration cycles selects the register of the configuration
space to access. Valid values are between 0 and 15, inclusive. Accessing registers outside this range results in an all-0s
value being returned on reads, and no action being taken on writes.
The Class Code register contains the Class Code, Sub-Class Code, and Register-Level Programming Interface registers.
All writable bits in the configuration space are reset to 0 by the hardware reset, PCI RESET (RST#) asserted. After reset, PCI-
680 is disabled and will only respond to PCI configuration write and PCI configuration read cycles.
1.11 Deviations from the Specification
The PCI-680 product has been developed and tested to the specification listed in this document. As a result of testing and
customer feedback, we may become aware of deviations to the specification that could affect the component's operation. To
ensure awareness of these deviations by anyone considering the use of the PCI-680, we will include them in this document.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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