SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
2.5 Power Supply Bypass Considerations
It is recommended that a 4-layer board (minimum) with internal Power and Ground Planes be used when i integrating the SiI
0680A . Good high-speed layout techniques should be used and proper power supply bypassing is essential. Both bulk and
local (high frequency) bypass capacitors should be used.
Bulk bypassing is intended to reduce the voltage noise (droop) induced by changes in load current and the inductance in the
power distribution system (wires and/or etch). Since the currents vary greatly from no activity to worst case data patterns, a
significant amount of capacitance is required.
All bypass capacitors should be connected to the power and ground plane with a low inductance connection (short, wide traces
connecting component pad to plane).
The bulk bypass capacitor(s) should have good high frequency characteristics. A capacitor with low ESR (Equivalent Series
Resistance) should be used. It should be located close to the source of +3.3V (output pin of regulator or connector pin for off
board regulators). The following minimum values are recommended:
Low ESR Tantalum – 100uF
Low ESR Aluminum Electrolytic – 600uF
Local high frequency 0bypass should also be implemented. Capacitors should be located on all four sides of the chip close to
the VDD/VSS pins. Three caps per side are recommended (12 total). Additional capacitors (x6) should be distributed evenly
around the board area.
The following capacitor is recommended for local bypass:
Ceramic X7R Dielectric - 0.01uF
For a slight improvement in high frequency impedance of the bypass capacitors, two capacitors in parallel can be used for
Local Bypass. The paired caps must be located as close as possible to each other. The following values are recommended
for the capacitor pairs:
Ceramic X7R Dielectric - 0.1uF
Ceramic X7R Dielectric – 1000pF
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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