SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
2.2 PCI 33 MHz Timing Specifications
Symbol
Parameter
Limits
Unit
Min
Max
TVAL
TVAL (PTP)
TON
CLK to Signal Valid – Bussed Signals
CLK to Signal Valid – Point to Point
Float to Active Delay
2.0
2.0
2.0
-
11.0
ns
ns
ns
ns
ns
ns
ns
11.0
-
TOFF
Active to Float Delay
28.0
TSU
Input Setup Time – Bussed Signals
Input Setup Time – Point to Point
Input Hold Time
7.0
10.0
0.0
-
-
-
TSU (PTP)
TH
Table 2-3: PCI 33 MHz Timing Specifications
2.3 ATA/ATAPI-6 Slew Rate Specifications
Symbol
Parameter
Condition
Limits
Unit
Min
Max
SRISE
Output Slew Rate – Rising
Output Slew Rate – Falling
Refer to ATA Specification for
specific test condition
requirements
Refer to ATA Specification for
specific test condition
requirements
0.4
1
V/ns
V/ns
0.4
1
SFALL
Table 2-4: ATA /ATAPI-6 Slew Rate Specifications
2.4 ATA/ATAPI-6 AC/DC Specifications
Symbol
Parameter
Condition
Limits
Unit
Min
4
Max
-
IOL
IOH
V+
V-
Output Sink Current
-
mA
μA
V
Output Source Current
Low-to-High Input Threshold
High-to-Low Input Threshold
Output Voltage High
-
400
1.5
1.0
-
-
2.0
1.5
-
V
-6 mA < IOUT < 3 mA
VDD - VDD+
V
VOH
VOL
0.51
0.3
Output Voltage Low
IOUT = 6 mA
-
0.51
V
Table 2-5: ATA/ATAPI-6 DC Specifications
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
15
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