SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
1.7 PCI Interface
The PCI-680 PCI interface is compliant with the PCI Local Bus Specification (Revision 2.2). PCI stands for Peripheral
Component Interconnect, a high-performance and robust interconnect bus that provides a processor-independent data path
between the CPU and high-speed peripherals. The PCI Specification is monitored by the PCI Special Interest Group (PCI-
SIG). The PCI-SIG is an unincorporated association of members of the microcomputer industry created to monitor and
enhance the development of PCI architecture and is governed by PCI-SIG bylaws (HTTP://www.pcisig.com/).
The PCI-680 can act as a PCI master and a PCI slave, and contains the PCI-680 PCI configuration space and internal
registers. When the PCI-680 needs to access shared memory, it becomes the bus master of the PCI bus and completes the
memory cycle without external intervention. In the mode when it acts as a bridge between the PCI bus and the IDE/ATA bus it
will behave as a PCI slave.
1.8 PCI Initialization
Generally, when a system initializes a module containing a PCI device, the configuration manager reads the configuration
space of each PCI device on the PCI bus. Hardware signals select a specific PCI device based on a bus number, a slot
number, and a function number. If a device that is addressed (via signal lines) responds to the configuration cycle by claiming
the bus, then that function's configuration space is read out from the device during the cycle. Since any PCI device can be a
multifunction device, every supported function's configuration space needs to be read from the device. Based on the
information read, the configuration manager will assign system resources to each supported function within the device.
Sometimes new information needs to be written into the function's configuration space. This is accomplished with a
configuration write cycle.
1.9 PCI Bus Operations
PCI-680 behaves either as a PCI master or a PCI slave device at any time and switches between these modes as required
during device operation.
As a PCI slave, the PCI-680 responds to the following PCI bus operations:
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I/O Read
I/O Write
Configuration Read
Configuration Write
Memory Read
Memory Write
All other PCI cycles are ignored by the PCI-680.
As a PCI master, the PCI-680 generates the following PCI bus operations:
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Memory Read Multiple
Memory Read Line
Memory Read
Memory Write
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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