Si3220/Si3225
Table 10. DC Characteristics (VDD, VDD1–VDD4 = 3.3 V)
(VDD, VDD1–VDD4 = 3.13 V to 3.47 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Symbol
Test Condition
Min
0.7 x V
—
Typ
—
Max
5.25
Unit
V
High Level Input Voltage
Low Level Input Voltage
V
IH
DD
V
—
0.3 x V
—
V
IL
DD
High Level Output
Voltage
V
I = 4 mA
V – 0.6
DD
—
V
OH
O
Low Level Output
Voltage
V
DTX, SDO, INT,
SDITHRU:
—
—
—
0.4
V
OL
I = –4 mA
O
BATSELa/b, RRDa/b,
—
0.72
GPOa/b, TRD1a/b, TRD2a/b:
I = –40 mA
O
SDITHRU internal pullup
resistance
35
—
—
—
50
63
11
—
—
—
kΩ
Ω
Relay Driver Source Imped-
ance
R
V
V
–V
= 3.13 V
DD4
OUT
DD1
IO < 28 mA
–V = 3.13 V
Relay Driver Sink Impedance
R
—
Ω
IN
DD1
DD4
IO < 85 mA
Input Leakage Current
I
±10
µA
L
Table 11. Switching Characteristics—General Inputs1
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF)
Parameter
Symbol
Min
—
Typ
—
Max
Unit
Rise Time, RESET
RESET Pulse Width, GCI Mode
t
5
ns
ns
µs
r
2
t
t
500
6
—
—
—
rl
rl
RESET Pulse Width, SPI Daisy Chain Mode
—
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VDD
–
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 kΩ per device.
Rev. 1.0
15
SILICONIMAGE [ Silicon image ]
