Si3220/Si3225
Table 12. Switching Characteristics—SPI
VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF
Parameter
Test
Symbol
Min
Typ
Max
Unit
Conditions
Cycle Time SCLK
t
62
—
—
—
—
—
—
—
—
—
—
25
25
20
20
ns
ns
ns
ns
ns
c
Rise Time, SCLK
t
r
Fall Time, SCLK
t
f
Delay Time, SCLK Fall to SDO Active
t
d1
d2
Delay Time, SCLK Fall to SDO
Transition
t
t
Delay Time, CS Rise to SDO Tri-state
Setup Time, CS to SCLK Fall
—
25
20
25
20
220
—
—
—
—
—
—
—
4
20
—
—
—
—
—
10
ns
ns
ns
ns
ns
ns
ns
d3
t
su1
Hold Time, CS to SCLK Rise
t
h1
Setup Time, SDI to SCLK Rise
Hold Time, SDI to SCLK Rise
Delay Time between Chip Selects
SDI to SDITHRU Propagation Delay
t
su2
t
h2
t
cs
t
d4
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD –0.4 V, VIL = 0.4 V
tc
tr
tf
SCLK
CS
tsu1
th1
tcs
tsu2
th2
SDI
td1
td3
td2
SDO
td4
SDITHRU
Figure 1. SPI Timing Diagram
16
Rev. 1.0
SILICONIMAGE [ Silicon image ]
