Si3220/Si3225
Table 13. Switching Characteristics—PCM Highway Interface
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, CL = 20 pF)
1
1
1
Parameter
Symbol
Test
Units
Min
Typ
Max
Conditions
PCLK Period
t
122
—
3906
ns
p
Valid PCLK Inputs
—
—
—
—
—
—
—
—
—
256
512
—
—
—
—
—
—
—
—
—
kHz
kHz
768
kHz
1.024
1.536
1.544
2.048
4.096
8.192
MHz
MHz
MHz
MHz
MHz
MHz
2
FSYNC Period
t
—
40
—
—
—
—
—
125
50
—
—
60
µs
%
fs
PCLK Duty Cycle Tolerance
PCLK Period Jitter Tolerance
Rise Time, PCLK
t
dty
t
±120
25
ns
ns
ns
ns
ns
jitter
t
—
r
Fall Time, PCLK
t
—
25
f
Delay Time, PCLK Rise to DTX Active
t
t
—
20
d1
d2
Delay Time, PCLK Rise to DTX
Transition
—
20
Delay Time, PCLK Rise to DTX
t
—
—
20
ns
d3
3
Tristate
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
FSYNC Pulse Width
t
25
20
25
20
—
—
—
—
—
—
—
ns
ns
ns
ns
su1
t
h1
t
—
su2
t
—
h2
t
t /2
125 µs–t
p
wfs
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL = 0.4 V.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Spec applies to PCLK fall to DTX tristate when that mode is selected.
Rev. 1.0
17
SILICONIMAGE [ Silicon image ]
