Si3220/Si3225
Table 5. AC Characteristics
(VDD, VDD1–VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
Overload Level
2.5
Figure 6
—
—
—
—
—
—
V
PK
Overload Compression
2-Wire – PCM
2-Wire – PCM or PCM – 2-Wire:
200 Hz to 3.4 kHz
1
–65
dB
dB
Single Frequency Distortion
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
200 Hz to 3.4 kHz
D/A or A/D 8-bit
—
—
—
–65
—
Figure 5
Signal-to-(Noise + Distortion)
2
Ratio
Active off-hook, and OHT, any Z
0 dBm0, Active off-hook, and
T
Audio Tone Generator Signal-to-
46
—
—
dB
2
Distortion Ratio
OHT, any Z
T
Intermodulation Distortion
—
–0.25
—
—
–41
+0.25
dB
dB
2
2-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
0 dBm 0
Gain Accuracy
Attenuation Distortion vs. Freq.
Group Delay vs. Frequency
Figure 7,8
Figure 9
—
—
—
—
—
—
—
—
—
—
3
1014 Hz sine wave,
reference level –10 dBm
Signal level:
Gain Tracking
3 dB to –37 dB
–37 dB to –50 dB
—
—
—
—
—
—
± 0.25
± 0.5
± 1.0
700
dB
dB
dB
µs
–50 dB to –60 dB
—
Round-Trip Group Delay
1014 Hz, Within same time-slot
600
Crosstalk between channels
0 dBm0,
TX or RX to TX
300 Hz to 3.4 kHz
—
—
—
—
—
±0.0005
–75
–75
—
dB
dB
dB
TX or RX to RX
Gain Step Increment
2-Wire Return Loss
Notes:
300 Hz to 3.4 kHz
4
Step size around 0 dB
200 Hz to 3.4 kHz
5
26
30
—
dB
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the
complete range. See “Audio Path Processing”.
5. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register
coefficients.
6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the
sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application.
10
Rev. 1.0
SILICONIMAGE [ Silicon image ]
