Si3056
Si3018/19/10
Register 4. Interrupt Source
Bit
Name
Type
D7
RDTI
R/W
D6
ROVI
R/W
D5
FDTI
R/W
D4
BTDI
R/W
D3
DODI LCSOI DLCSI
R/W R/W R/W
D2
D1
D0
POLI
R/W
Reset settings = 0000_0000
Bit Name
Function
7
RDTI Ring Detect Interrupt.
0 = A ring signal is not occurring.
1 = A ring signal is detected. If the RDTM (Register 3) and INTE (Register 2) bits are set a hard-
ware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared. The RDI
bit (Register 2) determines if this bit is set only at the beginning of a ring pulse, or at the end of a
ring pulse as well. This bit should be cleared after clearing the PDL bit (Register 6) because pow-
ering up the line-side device may cause this interrupt to be triggered.
6
5
ROVI Receive Overload Interrupt.
0 = An excessive input level on the receive pin is not occurring.
1 = An excessive input level on the receive pin is detected. If the ROVM and INTE bits are set a
hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it. This bit is
identical in function to the ROV bit (Register 17). Clearing this bit also clears the ROV bit.
FDTI
BTDI
Frame Detect Interrupt.
0 = Frame detect is established on the communications link.
1 = This bit is set when the communications link does not have frame lock. If the FDTM and INTE
bits are set, a hardware interrupt occurs on the AOUT/INT pin. Once set, this bit must be written
to a 0 to be cleared.
4
3
Billing Tone Detect Interrupt.
0 = A billing tone has not occurred.
1 = A billing tone has been detected. If the BTDM and INTE bits are set, a hardware interrupt
occurs on the AOUT/INT pin. This bit must be written to 0 to clear it.
DODI Drop Out Detect Interrupt.
0 = The line-side power supply has not collapsed.
1 = The line-side power supply has collapsed (The DOD bit in Register 19 has fired). If the
DODM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be
written to 0 to be cleared. This bit should be cleared after clearing the PDL bit (Register 6)
because powering as the line-side device can cause this interrupt to be triggered.
2
LCSOI Loop Current Sense Overload Interrupt.
0 = The LCS bits have not reached max value (all ones).
1 = The LCS bits have reached max value. If the LCSOM bit (Register 3) and the INTE bit are
set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to be cleared.
LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent sit-
uation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI inter-
rupt fires, the OPD bit should be checked to determine if an overcurrent situation exists.
52
Rev. 1.05
SILICON [ SILICON ]
