Si3056
Si3018/19/10
Register 8. PLL Divide N
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
N[7:0]
R/W
Reset settings = 0000_0000 (serial mode 0, 1)
Reset settings = 0001_0011 (serial mode 2)
Bit
Name
Function
7:0
N[7:0]
PLL N Divider.
Contains the (value –1) for determining the output frequency on PLL1.
Register 9. PLL Divide M
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
M[7:0]
R/W
Reset settings = 0000_0000
Bit
Name
Function
7:0
M[7:0]
PLL M Divider.
Contains the (value –1) for determining the output frequency on PLL1.
Register 10. DAA Control 3
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
DDL
R/W
Reset settings = 0000_0000
Bit Name
7:1 Reserved Read returns zero.
Function
0
DDL
Digital Data Loopback.
0 = Normal operation.
1 = Audio data received on SDI and loops it back out to SDO before the TX and RX filters.
Outputted data is identical to inputted data.
Rev. 1.05
55
SILICON [ SILICON ]
