Si3056
Si3018/19/10
Register 3. Interrupt Mask
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name RDTM ROVM FDTM BTDM DODM LCSOM DLCSM POLM
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
RDTM
Ring Detect Mask.
0 = A ring signal does not cause an interrupt on the AOUT/INT pin.
1 = A ring signal causes an interrupt on the AOUT/INT pin.
6
5
ROVM
FDTM
Receive Overload Mask.
0 = A receive overload does not cause an interrupt on the AOUT/INT pin.
1 = A receive overload causes an interrupt on the AOUT/INT pin.
Frame Detect Mask.
0 = The communications link achieving frame lock does not cause an interrupt on the AOUT/
INT pin.
1 = The communications link achieving frame lock causes an interrupt on the AOUT/INT pin.
4
3
2
1
0
BTDM
DODM
Billing Tone Detect Mask.
0 = A detected billing tone does not cause an interrupt on the AOUT/INT pin.
1 = A detected billing tone causes an interrupt on the AOUT/INT pin.
Drop Out Detect Mask.
0 = A line supply dropout does not cause an interrupt on the AOUT/INT pin.
1 = A line supply dropout causes an interrupt on the AOUT/INT pin.
LCSOM Loop Current Sense Overload Mask.
0 = An interrupt does not occur when the LCS bits are all 1s.
1 = An interrupt occurs when the LCS bits are all 1s.
DLCSM Delta Loop Current Sense Mask.
0 = An interrupt does not occur when the LCS bits change.
1 = An interrupt does occur when the LCS bits change.
POLM
Polarity Reversal Detect Mask.
Generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity
of TIP and RING was switched.
0 = A polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin.
1 = A polarity change on TIP and RING causes an interrupt on the AOUT/INT pin.
Rev. 1.05
51
SILICON [ SILICON ]
