Si3056
Si3018/19/10
6. Control Registers
Table 23. Register Summary
Register
1
Name
Bit 7
SR
Bit 6
Bit 5
Bit 4
Bit 3
PWME
Bit 2
Bit 1
IDL
Bit 0
SB
Control 1
PWMM[1:0]
2
3
4
5
Control 2
Interrupt Mask
Interrupt Source
DAA Control 1
INTE
RDTM
RDTI
INTP
ROVM
ROVI
WDTEN
BTDM
BTDI
OPOL
PDL
RDI
LCSOM
LCSOI
RDT
HBE
RXE
POLM
POLI
OH
FDTM
FDTI
RDTP
DODM
DODI
ONHM
PDN
DLCSM
DLCSI
OHE
RDTN
6
DAA Control 2
7
8
Sample Rate Control
PLL Divide N
SRC[3:0]
N[7:0]
9
PLL Divide M
M[7:0]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32–37
38
39
40
41
42
43
DAA Control 3
DDL
DCE
System-Side and Line-Side Revision
Line-Side Device Status
Line-Side Device Revision
Serial Interface Control
TX/RX Gain Control 1
International Control 1
International Control 2
International Control 3
International Control 4
Call Progress Rx Attenuation
Call Progress Tx Attenuation
Ring Validation Control 1
Ring Validation Control 2
Ring Validation Control 3
Resistor Calibration
DC Termination Control
Reserved
Loop Current Status
Line Voltage Status
AC Termination Control
DAA Control 4
Reserved
TX Gain Control 2
RX Gain Control 2
TX Gain Control 3
RX Gain Control 3
Reserved
Line Current/Voltage Threshold
Interrupt
LSID[3:0]
FDT
0
REVA[3:0]
LCS[4:0]
REVB[3:0]
SSEL[1:0]
NSLV[2:0]
FSD
RPOL
ARX[2:0]
RZ
TXM
ACT22
CALZ
ATX[2:0]
ACT2
RXM
OHS
IIRE
RT
BTD
MCAL
CALD
OPE
BTE
OVL
ROV
RFWE
DOD
OPD
ARM[7:0]
ATM[7:0]
RDLY[1:0]
RDLY[2]
RNGV
RMX[5:0]
RAS[5:0]
RTO[3:0]
RCC[2:0]
RCALS
RCALM
RCALD
MINI[1:0]
RCAL[3:0]
ILIM
DCV[1:0]
DCR
LCS2[7:0]
LVS[7:0]
FULL21
ACIM[3:0]1
FILT1
FULL1
FOH[1:0]
OHS2
LVFD1
TGA21
RGA21
TGA31
RGA31
TXG2[3:0]1
RXG2[3:0]1
TXG3[3:0]1
RXG3[3:0]1
CVT[7:0]1
CVI1
HYB1–8[7:0]
44
Line Current/Voltage Threshold
Interrupt Control
Programmable Hybrid Register 1–8
Reserved
CVS1
CVM1
GCE
CVP1
45–52
53–58
59
TB3
SQ1
SQ0
Spark Quenching Control
RG1
Notes:
1. Bit is available for Si3019 line-side device only.
2. Bit is available for Si3010 and Si3018 line-side device only.
48
Rev. 1.05
SILICON [ SILICON ]
