Si3056
Si3018/19/10
Register 1. Control 1
Bit
D7
SR
D6
D5
D4
D3
D2
D1
IDL
R/W
D0
SB
Name
Type
PWMM[1:0]
R/W
PWME
R/W
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
SR
Software Reset.
0 = Enables the DAA for normal operation.
1 = Sets all registers to their reset value.
Note: Bit automatically clears after being set.
6
Reserved Read returns zero.
5:4 PWMM[1:0] Pulse Width Modulation Mode.
Used to select the type of signal output on the call progress AOUT pin.
00 = PWM output is clocked at 16.384 MHz as a delta-sigma data stream. A local density of
1s and 0s tracks the combined transmit and receive signals.
01 = Balanced conventional PWM output signal has high and low portions of the modulated
pulse that are centered on the 16 kHz sample clock.
10 = Conventional PWM output signal returns to logic 0 at regular 32 kHz intervals and rises
at a time in the 32 kHz period proportional to its instantaneous amplitude.
11 = Reserved.
3
PWME
Pulse Width Modulation Enable.
Sums the transmit and receive audio paths and presents it as a CMOS digital-level output of
PWM data. Use the circuit in “Figure 18. AOUT PWM Circuit for Call Progress” .
0 = Pulse width modulation signal for AOUT disabled.
1 = Pulse width modulation signal for call progress analog output (AOUT) enabled.
2
1
Reserved Read returns zero.
IDL
Isolation Digital Loopback.
0 = Digital loopback across the isolation barrier is disabled.
1 = Enables digital loopback mode across the isolation barrier. The line-side device must be
enabled and off hook before setting this mode. This data path includes the TX and RX filters.
0
SB
Serial Digital Interface Mode.
0 = Operation is in 15-bit mode, and the LSB of the data field indicates that a secondary
frame is required.
1 = The serial port is operating in 16-bit mode and requires a secondary frame sync signal,
FC, to initiate control data reads/writes.
Rev. 1.05
49
SILICON [ SILICON ]
