Si3056
Si3018/19/10
Register 6. DAA Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
PDL
R/W
PDN
R/W
Reset settings = 0001_0000
Bit
7:5
4
Name
Reserved Read returns zero.
Function
PDL
Powerdown Line-Side Device.
0 = Normal operation. Program the clock generator before clearing this bit.
1 = Places the line-side device in lower power mode.
3
PDN
Powerdown System-Side Device.
0 = Normal operation.
1 = Powers down the system-side device. A pulse on RESET is required to restore normal
operation.
2:0
Reserved Read returns zero.
Register 7. Sample Rate Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
SRC[3:0]
R/W
Reset settings = 0000_0000
Bit Name
7:4 Reserved Read returns zero.
3:0 SRC[3:0] Sample Rate Control.
Function
Sets the sample rate of the line-side device.
0000 = 7200 Hz
0001 = 8000 Hz
0010 = 8229 Hz
0011 = 8400 Hz
0100 = 9000 Hz
0101 = 9600 Hz
0110 = 10286 Hz
0111 = 12000 Hz
1000 = 13714 Hz
1001 = 16000 Hz
1010–1111 = Reserved
54
Rev. 1.05
SILICON [ SILICON ]
