Si1000/1/2/3/4/5
SFR Definition 18.1. VDM0CN: VDD_MCU Supply Monitor Control
Bit
7
6
5
4
3
2
1
0
VDMEN VDDSTAT VDDOK Reserved Reserved Reserved
Name
Type
Reset
R/W
1
R
R
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Varies
Varies
SFR Page = 0x0; SFR Address = 0xFF
Bit
Name
Function
7
VDMEN
VDD_MCU Supply Monitor Enable.
This bit turns the VDD_MCU supply monitor circuit on/off. The VDD_MCU Supply
Monitor cannot generate system resets until it is also selected as a reset source in
register RSTSRC (SFR Definition 18.2).
0: VDD_MCU Supply Monitor Disabled.
1: VDD_MCU Supply Monitor Enabled.
6
5
VDDSTAT
VDDOK
VDD_MCU Supply Status.
This bit indicates the current power supply status.
0: VDD_MCU is at or below the V
1: VDD_MCU is above the V
threshold.
threshold.
RST
RST
VDD_MCU Supply Status (Early Warning).
This bit indicates the current power supply status.
0: VDD_MCU is at or below the V
threshold.
WARN
1: VDD_MCU is above the V
monitor threshold.
WARN
4:2
1:0
Reserved
Unused
Read = 000b. Must Write 000b.
Read = 00b. Write = Don’t Care.
18.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 4.4 for complete RST pin spec-
ifications. The external reset remains functional even when the device is in the low power Suspend and
Sleep Modes. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
18.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; otherwise,
this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it.
The missing clock detector reset is automatically disabled when the device is in the low power Suspend or
Sleep mode. Upon exit from either low power state, the enabled/disabled state of this reset source is
restored to its previous value. The state of the RST pin is unaffected by this reset.
Rev. 1.0
179
SILICON [ SILICON ]
