Si1000/1/2/3/4/5
18.2. Power-Fail (VDD_MCU Supply Monitor) Reset
Si1000/1/2/3/4/5 devices have a VDD_MCU Supply Monitor that is enabled and selected as a reset source
after each power-on or power-fail reset. When enabled and selected as a reset source, any power down
transition or power irregularity that causes VDD_MCU to drop below V
will cause the RST pin to be
RST
driven low and the CIP-51 will be held in a reset state (see Figure 18.3). When VDD_MCU returns to a
level above V , the CIP-51 will be released from the reset state.
RST
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and theVDD_MCU supply
monitor is enabled and selected as a reset source. The enable state of the VDD_MCU supply monitor and
its selection as a reset source is only altered by power-on and power-fail resets. For example, if the
VDD_MCU supply monitor is de-selected as a reset source and disabled by software, then a software
reset is performed, the VDD_MCU supply monitor will remain disabled and de-selected after the reset.
In battery-operated systems, the contents of RAM can be preserved near the end of the battery’s usable
life if the device is placed in sleep mode prior to a power-fail reset occurring. When the device is in sleep
mode, the power-fail reset is automatically disabled and the contents of RAM are preserved as long as the
VBAT supply does not fall below V
. A large capacitor can be used to hold the power supply voltage
POR
above V
while the user is replacing the battery. Upon waking from sleep mode, the enable and reset
POR
source select state of the VDD_MCU supply monitor are restored to the value last set by the user.
To allow software early notification that a power failure is about to occur, the VDDOK bit is cleared when
the VDD_MCU supply falls below the V
threshold. The VDDOK bit can be configured to generate an
WARN
interrupt. See Section “12. Interrupt Handler” on page 129 for more details.
Important Note: To protect the integrity of Flash contents, the VDD_MCU supply monitor must be
enabled and selected as a reset source if software contains routines which erase or write Flash
memory. If the VDD_MCU supply monitor is not enabled, any erase or write performed on Flash memory
will cause a Flash Error device reset.
VDD_MCU/DC+
VWARN
VRST
VBAT
VPOR
t
VDDOK
SLEEP
RST
Note: Wakeup signal
required after new
battery insertion
Sleep Mode
RAM Retained - No Reset
Active Mode
Power-Fail Reset
Figure 18.3. Power-Fail Reset Timing Diagram
Rev. 1.0
177
SILICON [ SILICON ]
