Si1000/1/2/3/4/5
SFR Definition 18.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
RTC0RE FERROR C0RSEF
SWRSF WDTRSF MCDRSF
PORSF
PINRSF
Name
Type
Reset
R/W
R
R/W
R/W
R
R/W
R/W
R
Varies
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Page = 0x0; SFR Address = 0xEF.
Bit
Name
Description
Write
Read
7
RTC0RE SmaRTClock Reset Enable 0: Disable SmaRTClock
Set to 1 if SmaRTClock
alarm or oscillator fail
caused the last reset.
and Flag
as a reset source.
1: Enable SmaRTClock as
a reset source.
6
5
FERROR Flash Error Reset Flag.
N/A
Set to 1 if Flash
read/write/erase error
caused the last reset.
C0RSEF Comparator0 Reset Enable 0: Disable Comparator0 as Set to 1 if Comparator0
and Flag.
a reset source.
caused the last reset.
1: Enable Comparator0 as
a reset source.
4
3
2
SWRSF Software Reset Force and
Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
Set to 1 if Watchdog Timer
overflow caused the last
reset.
MCDRSF Missing Clock Detector
0: Disable the MCD.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
(MCD) Enable and Flag.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
1
PORSF Power-On / Power-Fail
0: Disable the VDD_MCU Set to 1 anytime a power-
Reset Flag, and Power-Fail Supply Monitor as a reset on or V monitor reset
DD
2
Reset Enable.
source.
occurs.
1: Enable the VDD_MCU
Supply Monitor as a reset
3
source.
0
PINRSF HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD_MCU Supply Monitor is stabilized may generate a system reset.
Rev. 1.0
181
SILICON [ SILICON ]
