Si1000/1/2/3/4/5
Important Notes:
The Power-on Reset (POR) delay is not incurred after a VDD_MCU supply monitor reset. See Section
“4. Electrical Characteristics” on page 40 for complete electrical characteristics of the VDD_MCU
monitor.
Software should take care not to inadvertently disable the V Monitor as a reset source when writing
DD
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to '1' to keep the V Monitor enabled as a reset source.
DD
The VDD_MCU supply monitor must be enabled before selecting it as a reset source. Selecting the
VDD_MCU supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD_MCU supply monitor and selecting it as a reset source. See Section “4. Electrical Characteristics”
on page 40 for minimum VDD_MCU Supply Monitor turn-on time. No delay should be introduced in
systems where software contains routines that erase or write Flash memory. The procedure for
enabling the VDD_MCU supply monitor and selecting it as a reset source is shown below:
1. Enable the VDD_MCU Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the VDD_MCU Supply Monitor to stabilize (optional).
3. Select the VDD_MCU Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
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