Si1000/1/2/3/4/5
19. Clocking Sources
Si1000/1/2/3/4/5 devices include a programmable precision internal oscillator, an external oscillator drive
circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision internal
oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low power internal
oscillator is automatically enabled and disabled when selected and deselected as a clock source. SmaRT-
Clock operation is described in the SmaRTClock oscillator chapter.
The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low
power internal oscillator, or SmaRTClock oscillator. The global clock divider can generate a system clock
that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. Oscillator electrical
specifications can be found in the Electrical Specifications Chapter.
OSCICL
OSCICN
CLKSEL
Option 2
VDD
Option 3
XTAL2
XTAL2
EN
Precision
Internal Oscillator
Precision Internal Oscillator
External Oscillator
CLKRDY
Option 1
XTAL1
External
Oscillator
10M
Drive Circuit
n
SYSCLK
Low Power Internal Oscillator
smaRTClock Oscillator
XTAL2
Clock Divider
Option 4
XTAL2
smaRTClock
Oscillator
Low Power
Internal Oscillator
OSCXCN
Figure 19.1. Clocking Sources Block Diagram
The proper way of changing the system clock when both the clock source and the clock divide value are
being changed is as follows:
If switching from a fast “undivided” clock to a slower “undivided” clock:
1. Change the clock divide value.
2. Poll for CLKRDY > 1.
3. Change the clock source.
If switching from a slow “undivided” clock to a faster “undivided” clock:
1. Change the clock source.
2. Change the clock divide value.
3. Poll for CLKRDY > 1.
182
Rev. 1.0
SILICON [ SILICON ]
