Si1000/1/2/3/4/5
18. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
All SFRs are reset to the predefined values noted in the SFR descriptions. The contents of RAM are unaf-
fected during a reset; any previously stored data is preserved as long as power is not lost. Since the stack
pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
Monitor and power-on resets, the RST pin is driven low until the device
DD
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to an internal
oscillator. Refer to Section “19. Clocking Sources” on page 182 for information on selecting and configur-
ing the system clock source. The Watchdog Timer is enabled with the system clock divided by 12 as its
clock source (Section “28.4. Watchdog Timer Mode” on page 363 details the use of the Watchdog Timer).
Program execution begins at location 0x0000.
VDD_MCU/DC+
VBAT
*On Si1000/1/2/3 devices,
VBAT is internally
connected to VDD_MCU.
Power On
Reset
Supply
Monitor
(wired-OR)
Comparator 0
Px.x
Px.x
+
-
0
RST
+
-
Enable
C0RSEF
SmaRTClock
RTC0RE
Reset
Funnel
Missing
Clock
Detector
(one-
shot)
EN
PCA
WDT
(Software Reset)
SWRSF
EN
Illegal Flash
Operation
System
Clock
CIP-51
System Reset
System Reset
Microcontroller
Core
Power Management
Block (PMU0)
Power-On Reset
Reset
Extended Interrupt
Handler
Figure 18.1. Reset Sources
Rev. 1.0
175
SILICON [ SILICON ]
