EFR32MG13 Mighty Gecko Multi-Protocol Wireless SoC Family Data Sheet
Electrical Specifications
4.1.24 I2C
4.1.24.1 I2C Standard-mode (Sm)1
Table 4.55. I2C Standard-mode (Sm)1
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCL clock frequency2
SCL clock low time
SCL clock high time
SDA set-up time
fSCL
0
—
100
kHz
tLOW
4.7
4
—
—
—
—
—
—
—
µs
µs
ns
ns
µs
tHIGH
tSU_DAT
tHD_DAT
250
100
4.7
—
SDA hold time3
3450
—
Repeated START condition tSU_STA
set-up time
(Repeated) START condition tHD_STA
hold time
4
—
—
µs
STOP condition set-up time tSU_STO
4
—
—
—
—
µs
µs
Bus free time between a
tBUF
4.7
STOP and START condition
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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