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C8051F530-IM 参数 Datasheet PDF下载

C8051F530-IM图片预览
型号: C8051F530-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 8/4/2 KB ISP功能的Flash MCU系列 [8/4/2 kB ISP Flash MCU Family]
分类和应用:
文件页数/大小: 220 页 / 2701 K
品牌: SILICON [ SILICON ]
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C8051F52x-53x  
SFR Definition 11.4. EIP1: Extended Interrupt Priority 1  
R/W  
PMAT  
Bit7  
R/W  
PREG0  
Bit6  
R/W  
PLIN  
Bit5  
R/W  
PCPR  
Bit4  
R/W  
PCPF  
Bit3  
R/W  
PPAC0  
Bit2  
R/W  
R/W  
Reset Value  
PREG0 PWADC0 00000000  
Bit1  
Bit0  
SFR Address:  
0xF6  
Bit7:  
PMAT. Port Match Interrupt Priority Control.  
This bit sets the priority of the Port Match interrupt.  
0: Port Match interrupt set to low priority level.  
1: Port Match interrupt set to high priority level.  
PREG0: Voltage Regulator Interrupt Priority Control.  
This bit sets the priority of the Voltage Regulator interrupt.  
0: Voltage Regulator interrupt set to low priority level.  
1: Voltage Regulator interrupt set to high priority level.  
PLIN: LIN Interrupt Priority Control.  
This bit sets the priority of the CP0 interrupt.  
0: LIN interrupt set to low priority level.  
1: LIN interrupt set to high priority level.  
PCPR: Comparator Rising Edge Interrupt Priority Control.  
This bit sets the priority of the Rising Edge Comparator interrupt.  
0: Comparator interrupt set to low priority level.  
Bit6:  
Bit5:  
Bit4:  
Bit3:  
Bit2:  
Bit1:  
Bit0:  
1: Comparator interrupt set to high priority level.  
PCPF: Comparator falling Edge Interrupt Priority Control.  
This bit sets the priority of the Falling Edge Comparator interrupt.  
0: Comparator interrupt set to low priority level.  
1: Comparator interrupt set to high priority level.  
PPAC0: Programmable Counter Array (PCA0) Interrupt Priority Control.  
This bit sets the priority of the PCA0 interrupt.  
0: PCA0 interrupt set to low priority level.  
1: PCA0 interrupt set to high priority level.  
PREG0: ADC0 Conversion Complete Interrupt Priority Control.  
This bit sets the priority of the ADC0 Conversion Complete interrupt.  
0: ADC0 Conversion Complete interrupt set to low priority level.  
1: ADC0 Conversion Complete interrupt set to high priority level.  
PWADC0: ADC0 Window Comparison Interrupt Priority Control.  
This bit sets the priority of the ADC0 Window Comparison interrupt.  
0: ADC0 Window Comparison interrupt set to low priority level.  
1: ADC0 Window Comparison interrupt set to high priority level.  
96  
Rev. 0.3  
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