C8051F52x-53x
10.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 10.1 lists the SFRs
implemented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, IE, etc.) are bit-addressable
as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR
space are reserved for future use. Accessing these areas will have an indeterminate effect and should be
avoided. Refer to the corresponding pages of the data sheet, as indicated in Table 10.2, for a detailed
description of each register.
Table 10.1. Special Function Register (SFR) Memory Map
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
SPI0CN
B
PCA0L
PCA0H PCA0CPL0 PCA0CPH0
P1MDIN
VDDMON
RSTSRC
P0MDIN
EIP1
EIE1
ADC0CN
ACC
PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2
XBR0 XBR1 IT01CF
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2
PCA0CN
PSW
REF0CN
P0SKIP
TMR2L
P1SKIP
TMR2H
P0MAT
P1MAT
TMR2CN
REG0CN TMR2RLL TMR2RLH
ADC0GTL ADC0GTH ADC0LTL ADC0LTH P0MASK
IP
ADC0TK
OSCXCN OSCICN
CLKSEL
ADC0MX
OSCICL
ADC0CF
ADC0L
ADC0
P1MASK
FLKEY
OSCIFIN
IE
—
SCON0
P1
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT
SBUF0
CPT0CN
CPT0MD
LINCF
TH1
CPT0MX
LINADDR LINDATA
TCON
P0
TMOD
SP
TL0
DPL
2(A)
TL1
DPH
3(B)
TH0
4(C)
CKCON
6(E)
PSCTL
PCON
7(F)
0(8)
1(9)
5(D)
(bit addressable)
Rev. 0.3
87
SILICON [ SILICON ]
