C8051F52x-53x
10. Memory Organization and SFRs
The memory organization of the C8051F52x/F53x is similar to that of a standard 8051. There are two sep-
arate memory spaces: program memory and data memory. Program and data memory share the same
address space but are accessed via different instruction types. The memory map is shown in Figure 10.1.
PROGRAM/DATA MEMORY
DATA MEMORY (RAM)
(Flash)
INTERNAL DATA ADDRESS SPACE
‘F520/1 and ‘F530/1
0xFF
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
RESERVED
0x1E00
0x1DFF
0x80
0x7F
(Direct and Indirect
Addressing)
Lower 128 RAM
(Direct and Indirect
Addressing)
7680 Bytes Flash
0x30
0x2F
Bit Addressable
(In-System
Programmable in 512
Byte Sectors)
0x20
0x1F
General Purpose
Registers
0x00
0x0000
‘F526/7 and ‘F536/7
RESERVED
‘F523/4 and ‘F533/4
RESERVED
0x0800
0x07FF
0x1000
0x0FFF
2 kB Flash
4 kB Flash
(In-System
Programmable in 512
Byte Sectors)
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x0000
Figure 10.1. Memory Map
10.1. Program Memory
The CIP-51 core has a 64k-byte program memory space. The C8051F520/1 and ‘F530/1 implement 8 kB
of this program memory space as in-system, re-programmable Flash memory, organized in a contiguous
block from addresses 0x0000 to 0x1FFF. Addresses above 0x1DFF are reserved on the 8 kB devices. The
C8051F523/4 and ‘F533/4 implement 4 kB of Flash from addresses 0x0000 to 0x0FFF.The C8051F526/7
and ‘F536/7 implement 2 kB of Flash from addresses 0x0000 to 0x07FF.
Program memory is normally assumed to be read-only. However, the C8051F52x/F53x can write to pro-
gram memory by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX write instruc-
tion. This feature provides a mechanism for updates to program code and use of the program memory
space for non-volatile data storage. Refer to Section “13. Flash Memory” on page 107 for further details.
Rev. 0.3
85
SILICON [ SILICON ]
