C8051F52x-53x
SFR Definition 5.2. ADC0CF: ADC0 Configuration
R/W
Bit7
R/W
Bit6
R/W
AD0SC
Bit5
R/W
Bit4
R/W
Bit3
R/W
R/W
Bit1
R/W
ATTEN
Bit0
Reset Value
11111000
SFR Address:
0xBC
AD0RPT
Bit2
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers
to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock requirements are given in
Table 5.1.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is a maximum of 25 MHz, independent of the current system clock.
FCLK
CLKSAR
FCLK
AD0SC + 1
-------------------
----------------------------
=
AD0SC =
– 1 *
or
CLKSAR
*Note: Round the result up.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert
start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single
convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are set to a value other
than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
Bit0:
ATTEN: Attenuation Enabled Bit.
Controls the attenuation programming. For more information of the usage please refer to
the following chapter: Section “5.5. Selectable Attenuation” on page 57.
50
Rev. 0.3
SILICON [ SILICON ]
