C8051F52x-53x
P0.2
P0.1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
P0.3
P0.4/TX
P0.5/RX
P0.6/C2D
P0.7/XTAL1
P1.0/XTAL2
P1.1
RST/C2CK
P0.0/VREF
GND
VDD
VREGIN
P1.2/CNVSTR
P1.3
P1.7
P1.6
P1.5
P1.4
Table 4.2. Pin Definitions for the C8051F530 (TSSOP 20)
Name
Pin
Type Description
P0.2
D I/O or
A In
Port 0.2. See Port I/O Section for a complete description.
1
P0.1
D I/O or
A In
Port 0.1. See Port I/O Section for a complete description.
2
3
D I/O
Device Reset. Open-drain output of internal POR or V monitor. An
RST/
DD
external source can initiate a system reset by driving this pin low for at
least 15 µs. A 1 kΩ pullup to V is recommended. See Reset
DD
Sources Section for a complete description.
D I/O
C2CK
P0.0/
Clock signal for the C2 Debug Interface.
D I/O or
A In
Port 0.0. See Port I/O Section for a complete description.
4
V
A O or
D In
REF
External V
Ground.
Input. See V
Section.
REF
REF
GND
5
6
7
V
Core Supply Voltage.
DD
V
On-Chip Voltage Regulator Input.
REGIN
D I/O or
A In
Port 1.7. See Port I/O Section for a complete description.
P1.7
8
9
D I/O or
A In
Port 1.6. See Port I/O Section for a complete description.
P1.6
*Note: Please refer to Section “21. Revision Specific Behavior” on page 215.
Rev. 0.3
33
SILICON [ SILICON ]
