C8051F52x-53x
Table 4.2. Pin Definitions for the C8051F530 (TSSOP 20) (Continued)
Name
Pin
Type Description
D I/O or
A In
Port 1.5. See Port I/O Section for a complete description.
Port 1.4. See Port I/O Section for a complete description.
Port 1.3. See Port I/O Section for a complete description.
Port 1.2. See Port I/O Section for a complete description.
P1.5
10
D I/O or
A In
P1.4
11
12
D I/O or
A In
P1.3
P1.2/
D I/O or
A In
13
14
CNVSTR
D In
External Converter start input for the ADC0, see Section “5. 12-Bit
ADC (ADC0)” on page 41 for a complete description.
P1.1
D I/O or
A In
Port 1.1. See Port I/O Section for a complete description.
P1.0/
D I/O or
A In
Port 1.0. See Port I/O Section for a complete description.
External Clock Output. For an external crystal or resonator, this pin is
the excitation driver. This pin is the external clock input for CMOS,
capacitor, or RC oscillator configurations. See Section “15. Oscillators”
on page 133.
XTAL2
P0.7/
15
D I/O
D I/O or
A In
Port 0.7. See Port I/O Section for a complete description.
16
17
External Clock Input. This pin is the external oscillator return for a crys-
tal or resonator. Section “15. Oscillators” on page 133.
XTAL1
P0.6/
A In
D I/O or
A In
Port 0.6. See Port I/O Section for a complete description.
Bi-directional data signal for the C2 Debug Interface.
Port 0.5. See Port I/O Section for a complete description.
C2D
D I/O
P0.5/RX*
D I/O or
A In
18
19
20
P0.4/TX*
P0.3
D I/O or
A In
Port 0.4. See Port I/O Section for a complete description.
Port 0.3. See Port I/O Section for a complete description.
D I/O or
A In
*Note: Please refer to Section “21. Revision Specific Behavior” on page 215.
34
Rev. 0.3
SILICON [ SILICON ]
