C8051F52x-53x
SFR Definition 15.1. OSCICN: Internal Oscillator Control
R/W
R/W
R/W
R
R
-
R/W
IFCN2
Bit2
R/W
IFCN1
Bit1
R/W
IFCN0
Bit0
Reset Value
IOSCEN1 IOSCEN0 SUSPEND IFRDY
11000000
Bit7
Bit6
Bit5
Bit4
Bit3
SFR Address:
0xB2
Bit7–6: IOSCEN[1:0]: Internal Oscillator Enable Bits.
00: Oscillator Disabled.
01: Oscillator Enabled in Normal Mode and Disabled in Suspend Mode.
10: Oscillator Enabled in Normal Mode and Disabled in Suspend Mode.
11: Oscillator Enabled in Normal Mode and Disabled in Suspend Mode, Low Power.
SUSPEND: Internal Oscillator Suspend Enable Bit.
Setting this bit to logic 1 places the internal oscillator in SUSPEND mode. The internal oscil-
lator resumes operation when one of the SUSPEND mode awakening events occur.
IFRDY: Internal Oscillator Frequency Ready Flag.
0: Internal Oscillator is not running at programmed frequency.
1: Internal Oscillator is running at programmed frequency.
UNUSED. Read = 00b, Write = don't care.
Bit5:
Bit4:
Bits3:
Bits2–0: IFCN2–0: Internal Oscillator Frequency Control Bits.
000: SYSCLK derived from Internal Oscillator divided by 128 (default).
001: SYSCLK derived from Internal Oscillator divided by 64.
010: SYSCLK derived from Internal Oscillator divided by 32.
011: SYSCLK derived from Internal Oscillator divided by 16.
100: SYSCLK derived from Internal Oscillator divided by 8.
101: SYSCLK derived from Internal Oscillator divided by 4.
110: SYSCLK derived from Internal Oscillator divided by 2.
111: SYSCLK derived from Internal Oscillator divided by 1.
Rev. 0.3
135
SILICON [ SILICON ]
