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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
6.1. Modes of Operation  
In a typical system, ADC0 is configured using the following steps:  
1. If a gain adjustment is required, refer to Section “6.3. Selectable Gain” on page 58.  
2. Choose the start of conversion source.  
3. Choose Normal Mode or Burst Mode operation.  
4. If Burst Mode, choose the ADC0 Idle Power State and set the Power-Up Time.  
5. Choose the tracking mode. Note that Pre-Tracking Mode can only be used with Normal Mode.  
6. Calculate the required settling time and set the post convert-start tracking time using the AD0TK bits.  
7. Choose the repeat count.  
8. Choose the output word justification (Right-Justified or Left-Justified).  
9. Enable or disable the End of Conversion and Window Comparator Interrupts.  
6.1.1. Starting a Conversion  
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start  
of Conversion Mode bits (AD0CM10) in register ADC0CN. Conversions may be initiated by one of the fol-  
lowing:  
Writing a 1 to the AD0BUSY bit of register ADC0CN  
A rising edge on the CNVSTR input signal (pin P0.1)  
A Timer 1 overflow (i.e., timed continuous conversions)  
A Timer 2 overflow (i.e., timed continuous conversions)  
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-  
demand.” During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is  
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt  
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)  
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT  
is logic 1. Note that when Timer 2 overflows are used as the conversion source, Low Byte overflows are  
used if Timer2 is in 8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section  
“26. Timers” on page 265 for timer configuration.  
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.1. When the  
CNVSTR input is used as the ADC0 conversion source, Port pin P0.1 should be skipped by the Digital  
Crossbar. To configure the Crossbar to skip P0.1, set to 1 Bit1 in register P0SKIP. See Section “20. Port  
Input/Output” on page 177 for details on Port I/O configuration.  
6.1.2. Tracking Modes  
Each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accu-  
rate. ADC0 has three tracking modes: Pre-Tracking, Post-Tracking, and Dual-Tracking. Pre-Tracking Mode  
provides the minimum delay between the convert start signal and end of conversion by tracking continu-  
ously before the convert start signal. This mode requires software management in order to meet minimum  
tracking requirements. In Post-Tracking Mode, a programmable tracking time starts after the convert start  
signal and is managed by hardware. Dual-Tracking Mode maximizes tracking time by tracking before and  
after the convert start signal. Figure 6.2 shows examples of the three tracking modes.  
Pre-Tracking Mode is selected when AD0TM is set to 10b. Conversions are started immediately following  
the convert start signal. ADC0 is tracking continuously when not performing a conversion. Software must  
allow at least the minimum tracking time between each end of conversion and the next convert start signal.  
The minimum tracking time must also be met prior to the first convert start signal after ADC0 is enabled.  
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