C8051F50x-F51x
6. 12-Bit ADC (ADC0)
The ADC0 on the C8051F50x-F51x consists of an analog multiplexer (AMUX0) with 35/28 total input
selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-
hold, programmable window detector, programmable attenuation (1:2), and hardware accumulator. The
ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and accumu-
late samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0,
data conversion modes, and window detector are all configurable under software control via the Special
Function Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P3.7, the Temperature Sensor output, V , or GND with respect to GND. The voltage reference for
DD
ADC0 is selected as described in Section “7. Temperature Sensor” on page 72. ADC0 is enabled when the
AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
ADC0CN
ADC0MX
ADC0TK
*Available on 48-pin and
40-pin packages
00
01
10
11
AD0BUSY (W)
Start
Conversion
VDD
P0.0
Start
Conversion
Timer 1 Overflow
SYSCLK
Burst Mode
Logic
CNVSTR Input
Timer 2 Overflow
P0.7
P1.0
Burst Mode
Oscillator
25 MHz Max
12-Bit
SAR
P1.7
P2.0
Selectable
Gain
Accumulator
35-to-1
AMUX0
ADC
P2.7
P3.0
P3.1*
ADC0GNH ADC0GNL ADC0GNA
AD0WINT
Window
Compare
Logic
P3.7*
VDD
32
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
Temp Sensor
GND
ADC0CF
Figure 6.1. ADC0 Functional Block Diagram
52
Rev. 1.1
SILICON [ SILICON ]
