C8051F50x-F51x
Table 5.9. ADC0 Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified.
Parameter
DC Accuracy
Conditions
Min
Typ
Max
Units
Resolution
12
±0.5
±0.5
–1.8
bits
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
—
—
±3
±1
10
Guaranteed Monotonic
1
–10
Offset Error
Full Scale Error
–20
—
1.7
–2
20
—
LSB
Offset Temperature Coefficient
ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Conversion Rate
63
—
—
66
82
—
—
—
dB
dB
dB
Up to the 5th harmonic
–84
SAR Conversion Clock
—
—
—
3.6
—
MHz
2
13
clocks
Conversion Time in SAR Clocks
VDDA > 2.0 V
VDDA < 2.0 V
1.5
3.5
—
—
µs
3
Track/Hold Acquisition Time
VDDA > 2.0 V
4
—
—
200
ksps
Throughput Rate
Analog Inputs
gain = 1.0 (default)
gain = n
0
0
—
—
VREF
VREF/n
V
V
5
ADC Input Voltage Range
Absolute Pin Voltage with
Respect to GND
0
V
IO
Sampling Capacitance
Input Multiplexer Impedance
Power Specifications
—
—
32
3
—
pF
—
k
Operating Mode, 200 ksps
Power Supply Current
—
1100
1500
µA
(VDDA supplied to ADC0)
Burst Mode (Idle)
Power-On Time
—
5
1100
—
1500
—
µA
µs
dB
Power Supply Rejection Ratio
Notes:
—
-60
—
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed
through calibration.
2. An additional 2 FCLK cycles are required to start and complete a conversion
3. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section “6.2.1. Settling Time Requirements” on page 57.
4. An increase in tracking time will decrease the ADC throughput.
5. See Section “6.3. Selectable Gain” on page 58 for more information about the setting the gain.
Rev. 1.1
49
SILICON [ SILICON ]
