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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
Convert Start  
Pre-Tracking Mode  
S12 S13  
...  
Time  
F
S1  
S2  
F
ADC0 State  
AD0INT Flag  
Convert  
Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00')  
...  
Time  
ADC0 State  
AD0INT Flag  
F
S1  
S2 F F S1  
S2  
S12 S13  
F
Track  
Convert  
Key  
F
Equal to one period of FCLK.  
Each Sn is equal to one period of the SAR clock.  
Figure 6.3. 12-Bit ADC Tracking Mode Example  
Sn  
6.1.4. Burst Mode  
Burst Mode is a power saving feature that allows ADC0 to remain in a very low power state between con-  
versions. When Burst Mode is enabled, ADC0 wakes from a very low power state, accumulates 1, 4, 8, or  
16 samples using an internal Burst Mode clock (approximately 25 MHz), then re-enters a very low power  
state. Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conver-  
sions then enter a very low power state within a single system clock cycle, even if the system clock is slow  
(e.g., 32.768 kHz), or suspended.  
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0  
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set  
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after  
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered  
down, it will automatically power up and wait the programmable Power-Up Time controlled by the  
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 6.4 shows an exam-  
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.  
Important Note: When Burst Mode is enabled, only Post-Tracking and Dual-Tracking modes can be used.  
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat  
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,  
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have  
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