C8051F50x-F51x
Table 5.4. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
—
Typ
Max
Units
RST Output Low Voltage
VIO = 5 V; IOL = 70 µA
—
40
mV
0.7 x V
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
—
—
—
0.3 x V
115
IO
—
—
IO
RST = 0.0 V, VIO = 5 V
47
µA
V
V
V
RST Threshold (V
)
RST-LOW
1.65
2.25
1.75
2.30
1.80
DD
DD
RST Threshold (V
)
2.45
V
RST-HIGH
Time from last system clock
rising edge to reset initiation
Missing Clock Detector Timeout
Reset Time Delay
µs
VDD = 2.1V
VDD = 2.5V
200
200
370
270
600
600
Delay between release of
any reset source and code
execution at location 0x0000
—
6
130
—
160
—
µs
µs
Minimum RST Low Time to
Generate a System Reset
V
V
Monitor Turn-on Time
Monitor Supply Current
—
—
60
1
100
2
µs
DD
DD
µA
Table 5.5. Flash Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter
Flash Size
Conditions
Min
Typ
Max
Units
*
C8051F500/1/2/3/8/9
C8051F504/5/6/7-F510/1
65536
Bytes
32768
Endurance
20 k
10
150 k
—
—
—
Erase/Write
Years
ms
Flash Retention
Erase Cycle Time
Write Cycle Time
85 °C
25 MHz System Clock
25 MHz System Clock
28
30
45
79
84
125
µs
2
V
Write / Erase operations
—
—
V
V
DD
RST-HIGH
1. On the 64K Flash devices, 1024 bytes at addresses 0xFC00 to 0xFFFF are reserved.
2. See Table 5.4 for the V specification.
RST-HIGH
46
Rev. 1.1
SILICON [ SILICON ]
