C8051F50x-F51x
21.7.2. LIN Indirect Access SFR Registers Definitions
Table 21.4 lists the 15 indirect registers used to configured and communicate with the LIN controller.
Table 21.4. LIN Registers (Indirectly Addressable)
Name Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LIN0DT1
LIN0DT2
LIN0DT3
LIN0DT4
LIN0DT5
LIN0DT6
LIN0DT7
LIN0DT8
LIN0CTRL
LIN0ST
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
DATA1[7:0]
DATA2[7:0]
DATA3[7:0]
DATA4[7:0]
DATA5[7:0]
DATA67:0]
DATA7[7:0]
DATA8[7:0]
STOP(s) SLEEP(s)
TXRX
DTACK(s) RSTINT RSTERR WUPREQ STREQ(m)
ACTIVE IDLTOUT ABORT(s) DTREQ(s) LININT ERROR WAKEUP
DONE
LIN0ERR
LIN0SIZE
LIN0DIV
LIN0MUL
LIN0ID
SYNCH(s) PRTY(s)
TOUT
CHK
BITERR
ENHCHK
LINSIZE[3:0]
DIVLSB[7:0]
LINMUL[4:0]
PRESCL[1:0]
DIV9
ID0
ID5
ID4
ID3
ID2
ID1
Note: These registers are used in both master and slave mode. The register bits marked with (m) are accessible only in
Master mode while the register bits marked with (s) are accessible only in slave mode. All other registers are
accessible in both modes.
210
Rev. 1.1
SILICON [ SILICON ]
