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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
LIN Register Definition 21.7. LIN0ERR: LIN0 Error Register  
Bit  
7
6
5
4
3
2
1
0
SYNCH  
PRTY  
TOUT  
CHK  
BITERR  
Name  
Type  
Reset  
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Indirect Address = 0x0A  
Bit  
7:5  
4
Name  
Unused  
SYNCH  
Function  
Read = 000b; Write = Don’t Care  
Synchronization Error Bit (slave mode only).  
0: No error with the SYNCH FIELD has been detected.  
1: Edges of the SYNCH FIELD are outside of the maximum tolerance.  
3
2
PRTY  
TOUT  
Parity Error Bit (slave mode only).  
0: No parity error has been detected.  
1: A parity error has been detected.  
Timeout Error Bit.  
0: A timeout error has not been detected.  
1: A timeout error has been detected. This error is detected whenever one of the fol-  
lowing conditions is met:  
The master is expecting data from a slave and the slave does not respond.  
The slave is expecting data but no data is transmitted on the bus.  
A frame is not finished within the maximum frame length.  
The application does not set the DTACK bit (LIN0CTRL.4) or STOP bit  
(LIN0CTRL.7) until the end of the reception of the first byte after the identifier.  
1
0
CHK  
Checksum Error Bit.  
0: Checksum error has not been detected.  
1: Checksum error has been detected.  
BITERR  
Bit Transmission Error Bit.  
0: No error in transmission has been detected.  
1: The bit value monitored during transmission is different than the bit value sent.  
214  
Rev. 1.1  
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