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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
21.7. LIN Registers  
The following Special Function Registers (SFRs) and indirect registers are available for the LIN controller.  
21.7.1. LIN Direct Access SFR Registers Definitions  
SFR Definition 21.1. LIN0ADR: LIN0 Indirect Address Register  
Bit  
7
6
5
4
3
2
1
0
LIN0ADR[7:0]  
R/W  
Name  
Type  
Reset  
0
0
0
0
0
0
0
0
SFR Address = 0xD3; SFR Page = 0x00  
Bit Name  
7:0 LIN0ADR[7:0]  
Function  
LIN Indirect Address Register Bits.  
This register hold an 8-bit address used to indirectly access the LIN0 core registers.  
Table 21.4 lists the LIN0 core registers and their indirect addresses. Reads and  
writes to LIN0DAT will target the register indicated by the LIN0ADR bits.  
SFR Definition 21.2. LIN0DAT: LIN0 Indirect Data Register  
Bit  
7
6
5
4
3
2
1
0
LIN0DAT[7:0]  
R/W  
Name  
Type  
Reset  
0
0
0
0
0
0
0
0
SFR Address = 0xD2; SFR Page = 0x00  
Bit Name  
7:0 LIN0DAT[7:0]  
Function  
LIN Indirect Data Register Bits.  
When this register is read, it will read the contents of the LIN0 core register pointed  
to by LIN0ADR.  
When this register is written, it will write the value to the LIN0 core register pointed  
to by LIN0ADR.  
208  
Rev. 1.1