C8051F39x/37x
On the execution of the RETI instruction in the SPI0 ISR, the value in SFRPAGE register is overwritten
with the contents at the SFRPGIDX = 001b location. The CIP-51 may now access the TS0CN register as it
did prior to the interrupts occurring. See Figure 19.6.
SFRPGIDX[2:0]
1)SFR page 0x00 from SPI0 ISR automatically
popped off on return from interrupt
SFRPAGE = 0x0F
000
(TS0CN)
2)Value at SFRPGIDX = 001b location is
popped to SFRPAGE
001
010
011
100
SFRSTACK
Figure 19.6. SFR Page Stack Upon Return From SPI0 Interrupt
Push operations on the SFR page stack only occur on interrupt service, and pop operations only occur on
interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation
of the SFR page stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFRPGCN).
Preliminary Rev. 0.71
105
SILICON [ SILICON ]
