C8051F39x/37x
Table 19.2. Special Function Register (SFR) Memory Map
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
F8
F0
E8
SPI0CN PCA0L
P0MDIN
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 P1MAT
PCA0H PCA0CPL0 PCA0CPH0 P0MAT
P0MASK VDM0CN
EIP1 PCA0PWM
B
P1MDIN P2MDIN CKCON1
P1MASK RSTSRC
0
F
SMB0ADM
EIE1
E0
D8
D0
ACC
XBR0
XBR1
OSCLCN
IT01CF
SMB1ADM
PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 CRC0AUTO CRC0CNT CRC0CN
0
F
TS0DATL TS0DATH
TS0CN SFRSTACK
TMR2RLL TMR2RLH
TMR5RLL TMR5RLH
SMB0ADR
SMB1ADR
PSW
REF0CN
REG0CN
P0SKIP
P1SKIP
P2SKIP
TMR2CN
TMR5CN
TMR2L
TMR5L
TMR2H
TMR5H
C8
C0
PCA0CLR SFRPGCN
0 SMB0CN SMB0CF SMB0DAT
F SMB1CN SMB1CF SMB1DAT
ADC0GTL ADC0GTH ADC0LTL ADC0LTH
SMBTC
0
F
IDA0CN
IDA1CN
B8
B0
A8
IP
AMX0N
AMX0P
OSCICL
ADC0CF
ADC0L
ADC0H
FLSCL
EIP2
FLKEY
EIE2
OSCXCN OSCICN
CLKSEL EMI0CN
PFE0CN
0
F
DERIVID REVISION
SN0 SN1
IE
SN2
SN3
A0
98
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT SFRPAGE
SCON0
SBUF0 CRC0FLIP CPT0CN
TMR3CN TMR3RLL TMR3RLH
TMR4CN TMR4RLL TMR4RLH
CRC0IN
TMR3L
TMR4L
TH0
CPT0MD CRC0DAT CPT0MX
0
F
TMR3H
TMR4H
TH1
IDA0L
IDA1L
CKCON
EIP2H
6(E)
IDA0H
IDA1H
PSCTL
PCON
7(F)
90
P1
88
80
TCON
P0
TMOD
SP
TL0
DPL
2(A)
TL1
DPH
3(B)
IPH
EIP1H
5(D)
0(8)
1(9)
4(C)
Notes:
1. SFR Addresses ending in 0x0 or 0x8 are bit-addressable locations and can be used with bitwise instructions.
2. Unless indicated otherwise, SFRs are available on both page 0 and page F.
Preliminary Rev. 0.71
109
SILICON [ SILICON ]
