C8051F39x/37x
The SPI0 interrupt occurs while the core executes in-line code by writing a value to TS0CN. The core vec-
tors to the SPI0 ISR and pushes the current SFR page value (in this case SFR page 0x0F for TS0CN) into
the 001b SFRPGIDX location in the SFR page stack. Also, the core automatically places the SFR page
(0x00) needed to access the SPI0’s special function registers into the SFRPAGE register. See Figure 19.3.
SFRPAGE is considered the top of the SFR page stack. Software may switch to any SFR page by writing
a new value to the SFRPAGE register at any time during the SPI0 ISR.
SFRPGIDX[2:0]
2) SFRPAGE automatically set
to 0x00 on SPI0 interrupt
SFRPAGE = 0x00
000
(SPIO0)
0x0F
1) SFRPAGE is pushed to
SFRPGIDX = 001b location
001
010
011
100
(TS0CN)
SFRSTACK
Figure 19.3. SFR Page Stack After SPI0 Interrupt Occurs
102
Preliminary Rev. 0.71
SILICON [ SILICON ]
