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C8051F390-A-GM 参数 Datasheet PDF下载

C8051F390-A-GM图片预览
型号: C8051F390-A-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 50 MIPS 16 KB的闪存, 512B EEPROM混合信号MCU [50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU]
分类和应用: 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 300 页 / 1709 K
品牌: SILICON [ SILICON ]
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C8051F39x/37x  
On exit from the PCA0 interrupt service routine, the CIP-51 will return to the SPI0 ISR. On execution of the  
RETI instruction, SFR page 0x00 used to access the PCA0 registers will be automatically popped off of the  
SFR page stack, and the contents at the SFRPGIDX = 001b location will be moved to the SFRPAGE reg-  
ister. Software in the SPI0 ISR can continue to access SFRs as it did prior to the PCA interrupt. Likewise,  
the contents at the SFRPGIDX = 010b location are moved to the SFRPGIDX = 001b location. Recall this  
was the SFR Page value 0x0F being used to access TS0CN before the SPI0 interrupt occurred. See  
Figure 19.5.  
SFRPGIDX[2:0]  
1)SFR page 0x00 from PCA0 ISR automatically  
popped off on return from interrupt  
SFRPAGE = 0x00  
000  
(SPI0)  
0x0F  
2)Value at SFRPGIDX = 001b location is  
popped to SFRPAGE  
001  
010  
011  
100  
(TS0CN)  
3)Value at SFRPGIDX = 001b location is  
popped to SFRPGIDX = 010b location  
SFRSTACK  
Figure 19.5. SFR Page Stack Upon Return from PCA0 Interrupt  
104  
Preliminary Rev. 0.71  
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