C8051F39x/37x
19.3. SFR Page Stack Example
In this example, the SFR Control register is left in the default enabled state (SFRPGEN set to 1), and the
core is executing in-line code that is writing values to Temperature Sensor Control Register (TS0CN). The
device is also using the SPI peripheral (SPI0) and the Programmable Counter Array (PCA0) peripheral to
generate a PWM output. The PCA is timing a critical control function in its interrupt service routine, there-
fore, its associated ISR is set to high priority. At this point, the SFR page is set to 0x0F to access the
TS0CN SFR. See Figure 19.2.
SFRPGIDX[2:0]
SFRPAGE = 0x0F
000
(TS0CN)
001
SFRSTACK
010
011
100
Figure 19.2. SFR Page Stack While Using SFR Page 0x0F To Access TS0CN
Preliminary Rev. 0.71
101
SILICON [ SILICON ]
